As shown in the diagram, a PMOS transistor is used as the high-side switch, and an NMOS transistor is used as the low-side switch. Both of these drive circuits can effectively control the operation of the load.

But why is PMOS usually placed on the high side and NMOS on the low side?

MOS transistors, as switches, can be placed either in front of or behind the load. This is determined by the different conditions for turning on the two types of switches.

There are generally two situations: high-side driving, where the MOS switch is directly connected to the power supply, and low-side driving, where the MOS switch is connected to ground.

Let's look at the conduction conditions for both:

Enhancement-mode NMOS: The voltage difference between GS (gate and source) needs to be greater than the threshold voltage Vgs(th).

When NMOS is placed on the low side, with the source connected to GND, conduction occurs when the gate voltage is higher than 0 and exceeds the threshold.

Enhancement-mode PMOS: It's exactly the opposite of NMOS. The voltage difference between GS needs to be less than the threshold voltage Vgs(th).

When PMOS is placed on the high side, with the source connected to Vbat, conduction occurs when the gate voltage is lower than Vbat and the difference exceeds the threshold.

What if the positions of NMOS and PMOS are swapped?

Due to the floating potential of the reference S junction, controlling the gate voltage becomes relatively complex.

Here's a circuit design example:

By controlling the power circuit on/off through MCU (Microcontroller Unit), the output voltage Vo can be set to be equal to Vbat or 0 at any time, thereby controlling the power supply to the subsequent load circuit.

First, Vbat voltage is fixed, and Vo and the subsequent stage voltage are variable.

We use HSD high-side driving to control the switch. PMOS is preferred for high-side driving control, requiring only the gate voltage to be slightly lower than Vbat. (If NMOS is used, consideration needs to be given to providing a gate control signal higher than Vbat).

In the diagram, resistor R1 is used to ensure the voltage difference between GS.

It is important to note the connection of PMOS. The source must be connected to the fixed potential of Vbat. If it is reversed, the body diode will conduct directly, losing control ability.

Next, how to control the gate of PMOS to achieve the change of two voltage states?

We can consider using a voltage divider:

Adding resistor R2, when the small switch is open, the bottom of R2 is suspended. The gate voltage of PMOS is VBAT due to R1, VGS=0, and PMOS remains off.

If you want to control this small switch, just use a transistor. MCU controls its base. When the MCU input is low, the transistor cannot conduct, the bottom of R2 is suspended, and PMOS remains off; when the MCU input is high, the transistor conducts, R2 is connected to ground through the transistor, achieving voltage division and lowering the gate voltage of P-channel transistor, eventually turning it on.

Key points for this circuit design:

1. There is a PN junction between the base and emitter of the transistor, resulting in a conduction voltage drop (about 0.7V). When calculating the gate voltage of PMOS, this 0.7V should be taken into account in the voltage division of R1 and R2.

2. R3 is used to limit the input current Ibe of the transistor, and R4 ensures that the base voltage is 0 when the MCU pin is floating, effectively turning off the transistor.

3. The diode D1, connected in parallel with R1, serves to protect the MOS transistor, preventing damage to the MOS due to an abnormal overvoltage of the external power supply VBAT, exceeding the maximum allowed voltage between GS of the MOS.

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(Disclaimer：The above information and images are sourced from the internet.)

That concludes the content for this issue! Thank you for reading and supporting!